1. Field of the Invention
This invention relates generally to the structure and fabrication process of semiconductor transistors. More particularly, this invention relates to a novel and improved power transistor gate contact design and configuration in order to prevent the contact metal from penetrating the gate layer without adversely affecting the breakdown voltage in the gate runner whereby the reliability difficulties and product yield problems caused by contract metal penetration through the gate layer may be resolved.
2. Description of the Prior Art
The problem of gate-drain short and gate-source short in the gate contact areas, e.g., in a contact area on a polysilicon finger, for a power device is becoming more pronounced due to several factors. One of a most important reasons for this problem is the fact that the gate employed in the semiconductor power devices is becoming more and more heavily doped with ions such as arsenic, phosphorous, boron or POCL.sub.3 dopants to achieve higher switching speed. However, more processing defects such as the etching pits are increased as the gate layer becomes more heavily doped. Additionally, since the thickness of the gate is decreased to increase the metal step coverage in the contact area, the contact metal formed above the polysilicon gate, i.e., "poly" gate, in entering to gate layer through these processing defects, has greater degree of likelihood that the contact metal may penetrate through this thin poly gate layer and a thin gate oxide layer underneath thus forming a short circuit connecting the contact to the substrate drain and the source underneath the gate layer. As the devices are further miniaturized and the gate layer is becoming thinner while the gate is ever heavier doped to improve device performance, this concern of contact metal penetration through gate has increasingly caused difficulties in product reliability and production yield.
In order to better understand the background of this invention, please refer to FIG. 1 which is a partial top view of the MOSFET device 10 with the active area 40 which includes core cell areas 42 and gate contact areas 44 as shown. There are a plurality of cells each includes source contact 30 surrounded by p-body 25 and the cells are arranged in a square-on-square configuration. The polysilicon gates are extended as "poly-fingers" 72 from the core cell area 40 outwardly to the gate contact area 44 with a gate runner 76 connected to these poly fingers 72 with a plurality of gate contacts, i.e., poly contact 70 formed thereon. There are no rigid rules governing the locations of the gate contacts 70. The MOSFET device 10 also includes field oxide area 50 opposite the active area 40 as will be further discussed below in FIG. 2A.
FIG. 2A shows a cross-sectional view along the lines of X-X' in FIG. 1 for the conventional N-channel MOSFET device 10. The MOSFET device 10 is supported on a n.sup.+ substrate 15 with a n.sup.- doped epitaxial drain region 20 formed thereon. A plurality of p-body regions 25 and n.sup.+ source regions 30 are formed on top of the drain region 20 as shown. The MOSFET device 10 is divided into an active area 40 which includes a core cell area 42 and a gate contact area 44. The MOSFET device 10 further includes a field oxide area 50. A plurality of cells which include the p-body 25, the source regions 30, and a polysilicon gate 35 are formed in the core cell area 42. As shown in FIG. 1, the source electrode (S) 60 is formed in the core cell area 42 and the gate runner (G) 76 and the gate contacts 70 are formed in the gate contact areas 44 in the active area 40 near the field oxide areas 50. The field plate (FP) 80 and the equal ring (EQR) 90 are formed in the filed oxide area 50 where the field oxide layer 52 is not removed in the manufacturing process.
Due to the fact that the polysilicon gate 35 is now more heavily doped, the contact metal deposited on top of the gate layer 35 tends to have higher possibility to penetrate through the polysilicon layer 35 due to more defects formed in a contact etch process in forming the contact openings above the gate layer to deposit the contact metal therein. The contact metals can easily enter into the small cracks on the gate layer 35. As the polysilicon gate 35 has a thickness of about half a micron or less while the gate oxide layer 39 underneath the gate layer 35 has a thickness ranging between 100 to 1000 Angstroms, the metal contacts, e.g., aluminum, often penetrates the gate layer 35 and the gate oxide layer 39 as that shown in FIG. 2B. A gate-to-drain and gate-to-source short circuits maybe formed due to such penetration and various performance characteristics are adversely affected when this short circuit occurs. The product reliability and production yield are therefore affected by this gate-metal penetrating through gate phenomenon.
In a conventional method of manufacturing the semiconductor device, the gate oxide 37 under the polysilicon gate 35 and the oxide layer 39 below the gate contact 70 underneath the polysilicon gate are formed as a single layer with uniform thickness. The manufacture process is simplified to form a gate oxide layer 37 and 39 over the entire area. However, as the device performance would generally be improved with a thinner gate oxide, the oxide layer 39 below the gate contact 70 is also made very thin just like the gate oxide 37 in the core cells. A person of ordinary skill in the art would generally apply this manufacture process for the very reason that the manufacture process is simpler and the penetration phenomenon of the contact metals through the gate 35 and the oxide layer 39 are not yet fully studied and the real cause of the problems associated with poor product reliability and product yield are still not clearly identified.
FIG. 2B is a scanning electronic microscopic (SEM) cross sectional picture of a conventional gate structure to clearly depict the root cause of the gate contact problems. The picture dear shows that the contact metal penetrates the gate layer and the gate oxide layer underneath. Without detail diagnostic test in a highly sophisticate laboratory to discover the penetration of the metal through the gate and the gate oxide, those of ordinary skill in the art in design and manufacturing the semiconductor device are still in search of the real cause of the technical difficulties. A solution to the problems associate with the penetration phenomenon cannot be defined yet because the real reasons lead to the problems are not yet determined.
Therefore, a need still exists in the art of power device fabrication, particularly for semiconductor power device design and fabrication, to provide an improved gate structure and fabrication process that would resolve these difficulties.